DocumentCode
2742336
Title
The application of novel failure analysis techniques for advanced multi-layered CMOS devices
Author
Hong, Yeoh Eng ; We, Martin Tay Tiong
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
1997
fDate
1-6 Nov 1997
Firstpage
304
Lastpage
309
Abstract
The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection. Without these tools, FA on extremely complex devices such as microprocessors will be extremely difficult, if not impossible.
Keywords
CMOS digital integrated circuits; design for testability; failure analysis; fault location; integrated circuit testing; logic testing; DFT; assembly code programming; defect detection; design for testability; failure analysis; fault localisation; functional model simulation; logic testing; microprocessors; multi-layered CMOS devices; Assembly; Buildings; CMOS technology; Circuit faults; Design for testability; Failure analysis; Functional programming; Integrated circuit interconnections; Microprocessors; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1997. Proceedings., International
ISSN
1089-3539
Print_ISBN
0-7803-4209-7
Type
conf
DOI
10.1109/TEST.1997.639631
Filename
639631
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