Design re-use: where is the productivity going to come from?

Semiconductor process geometries are shrinking and the available silicon capacity is growing at an amazing pace. Consumerization and convergence applications are causing tremendous time to market pressures, resulting in increased product complexity and reduced design cycle times. The gap between what can be built (silicon capacity) and what can be designed is widening. This `design productivity gap´ is causing an industry-wide shift to system-on-a-chip (SOC) design methodology. The corner-stone for success of the SOC methodology is design re-use. The methodology for design re-use will evolve going forward. Huge investments will be made to setup infrastructure and methodologies for creation of re-usable designs and their integration into future products. But, will they deliver the expected productivity gains? This talk presents a progression of re-use methodology alternatives and the key characteristics and productivity impact of each approach