DocumentCode
2742519
Title
Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM´s
Author
Urakawa, Y. ; Matsui, M. ; Suzuki, A. ; Kato, H. ; Hamano, T. ; Sato, K. ; Ohtani, T. ; Ochii, K.
Author_Institution
TOSHIBA Corp.
fYear
1991
fDate
May 30 1991-June 1 1991
Firstpage
19
Lastpage
20
Keywords
BiCMOS integrated circuits; Bipolar transistors; Clamps; Degradation; Delay; Equalizers; Laboratories; Random access memory; Ultra large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1991. Digest of Technical Papers. 1991 Symposium on
Conference_Location
Oiso, Japan
Type
conf
DOI
10.1109/VLSIC.1991.760058
Filename
760058
Link To Document