A 3–5GHz UWB CMOS receiver with digital control technique

Author

Han, Bo ; Liu, Mengmeng ; Ge, Ning

Author_Institution

Dept. of Microelectron., Electron. Eng., Tsinghua Univ., Beijing, China

fYear

2010

fDate

14-16 April 2010

Firstpage

157

Lastpage

160

Abstract

This article presents a CMOS receiver that works for 3-5GHz low band SC-UWB. The receiver contains PLL, Mixer, and VGA. Double down conversion is adopted in the receiver to overcome the orthogonal clock design difficulty; digital assisted RF control method is used to increase the stability. This receiver was fabricated in SMIC01.8mmRF process with chip area of 1 × 1 mm² ;according to measurement, this receiver has bandwidth of 500MHz; VGA control range is 30dB; IIP3 is -10dBm;IF port output is 250mVp-p; the power consumption is 36mW with supplying voltage 1.8V.

Keywords

CMOS analogue integrated circuits; amplifiers; mixers (circuits); phase locked loops; ultra wideband technology; PLL; SC-UWB; SIC01.8mmRF process; UWB CMOS receiver; VGA control range; bandwidth 500 MHz; digital assisted RF control; digital control technique; double down conversion; frequency 3.5 GHz; mixer; power 36 mW; voltage 1.8 V; Area measurement; Bandwidth; Clocks; Digital control; Phase locked loops; Power measurement; Radio frequency; Semiconductor device measurement; Stability; Voltage control; Digital-assisted RF; UWB; VGA;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Conference_Location

Vienna

Print_ISBN

978-1-4244-6612-2

Type

conf

DOI

10.1109/DDECS.2010.5491794

Filename

5491794