An algorithm for hierarchical floorplan design

Author

Wong, D.F. ; The, K.-S.

Author_Institution

Dept. of Comput. Sci., Texas Univ., TX, USA

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

484

Lastpage

487

Abstract

A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu´s, and improvement was obtained in the test samples.<>

Keywords

VLSI; circuit layout CAD; optimisation; 2-5 Polish expressions; cost function evaluations; floorplan area optimization algorithm; hierarchical floorplan design; neighborhood structure; neighboring solutions; nonslicing floorplans; order-5 hierarchical floorplan; search technique; simulated annealing; Algorithm design and analysis; Area measurement; Circuit testing; Computer simulation; Cost function; Design optimization; Integrated circuit interconnections; Simulated annealing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76996

Filename

76996