DocumentCode
274325
Title
Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout
Author
Luk, W.K. ; Dean, A.A. ; Mathews, J.W.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
492
Lastpage
495
Abstract
A method is presented for floorplanning data-path chips by a technique of multi-terrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.<>
Keywords
VLSI; circuit layout CAD; microprocessor chips; data-path chip; floor-planning; floorplanning; integrated global wiring; microprocessor data path layout; multi-terrain partitioning; multistack placement; standard-cell placement; terrain shape; terrain size; timing; wirability; Chip scale packaging; Logic arrays; Microprocessors; Multiplexing; Registers; Shape control; Size control; Timing; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76998
Filename
76998
Link To Document