An asynchronous communication protocol for heterogeneous digital signal processing systems

Author

Khan, Mohammad S. ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

2

fYear

1994

fDate

3-5 Aug 1994

Firstpage

761

Abstract

This paper describes an asynchronous communication protocol and the architecture of the interface control unit which is used for building heterogeneous digital signal processing systems from an inventory of heterogeneous building blocks. The communication protocol is designed to curtail overhead incurred by the control processor and distribute the control to individual nodes of a cluster. Implementation of the hardware is achieved by separating the control circuitry of individual data queues and permitting the occurrence of concurrent operations independently

Keywords

multiprocessor interconnection networks; peripheral interfaces; protocols; signal processing; FIFO buffers; ICU protocol; asynchronous communication protocol; cluster nodes; communication channel interface protocol; concurrent operations; data packet format; data queues; data transfer sequencing; heterogeneous digital signal processing systems; interface control unit architecture; Asynchronous communication; Buildings; Circuits; Communication switching; Communication system control; Control systems; Digital signal processing; Hardware; Integrated circuit interconnections; Process control; Protocols; Signal processing; Switches; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.518927

Filename

518927