DocumentCode
2745084
Title
Logical diagnosis solutions must drive yield improvement
Author
Ryan, Paul G.
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
1997
fDate
1-6 Nov 1997
Firstpage
434
Abstract
The author discusses automated production-worthy solutions for high-volume manufacturing. He suggests that Design for Test (DFT) techniques such as scan (particularly full scan) provide design hooks that enable more effective solutions, while advances in realistic defect behavior modeling and simulation are improving both the accuracy and the ability to localize more difficult defect types. Given a real commitment and a significant investment in research and development, the logic diagnosis problem is promising
Keywords
automatic testing; design for testability; fault diagnosis; integrated circuit testing; integrated circuit yield; logic design; logic testing; production testing; DFT; Design for Test; defect behavior modeling; failure diagnosis; full scan; logic diagnosis; simulation; yield analysis; yield improvement; Costs; Fading; Failure analysis; Geometry; Logic testing; Manufacturing; Production; Silicon; Stress; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1997. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-4209-7
Type
conf
DOI
10.1109/TEST.1997.639647
Filename
639647
Link To Document