Delay testing with clock control: an alternative to enhanced scan

Path delay fault testing in non-scan sequential circuits is complicated by the limited state transitions during normal operation. An accepted method for overcoming this difficulty is to use a scan chain consisting of enhanced scan flip-flops which makes the application of arbitrary vector pairs possible. However, the method results in increased path delays because of the enhanced scan flip-flops themselves. In this paper we present a new method for improving path delay fault testability without increasing path delays in the circuit. It uses a simple clock control circuit to produce single bit transitions on state variables and a parity check circuit for observing state variable flip-flops. The area overhead of this method is comparable to enhanced scan but no performance penalty is incurred. We demonstrate the effectiveness of this method in delay testing and show how it can be used for stuck-at fault testing