Joint source-channel coding using finite state integer arithmetic codes

Author

Moradmand, Hashem ; Payandeh, Ali ; Aref, Mohammad Reza

Author_Institution

Electr. & Electron. Eng. Center, MUT, Tehran, Iran

fYear

2009

fDate

7-9 June 2009

Firstpage

19

Lastpage

22

Abstract

Inserting redundancy to arithmetic codes is a common strategy to add error detection capability to this well-known family of source codes. By using this strategy error correction is possible through some decoding algorithms such as Viterbi decoder. In this paper a system has proposed that uses finite state integer arithmetic codes (FSAC) as a joint source-channel code in combination with a cyclic redundancy check (CRC) and a List Viterbi decoder. The proposed scheme has shown better performance than previous ones.

Keywords

Viterbi decoding; arithmetic codes; channel coding; cyclic redundancy check codes; finite state machines; source coding; List Viterbi decoder; cyclic redundancy check; finite state integer arithmetic codes; joint source-channel coding; Arithmetic; Automata; Channel coding; Cyclic redundancy check; Cyclic redundancy check codes; Decoding; Delay; Error correction; Source coding; Viterbi algorithm; arithmetic coding; compression; finite state machine; joint source channel coding; list Viterbi decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Electro/Information Technology, 2009. eit '09. IEEE International Conference on

Conference_Location

Windsor, ON

Print_ISBN

978-1-4244-3354-4

Electronic_ISBN

978-1-4244-3355-1

Type

conf

DOI

10.1109/EIT.2009.5189577

Filename

5189577