DocumentCode
2747078
Title
A charge coupled device architecture for on focal plane image signal processing
Author
Yang, Woodward
Author_Institution
Artificial Intelligence Lab., MIT, Cambridge, MA, USA
fYear
1989
fDate
17-19 May 1989
Firstpage
266
Lastpage
270
Abstract
A parallel, pipelined architecture for performing real-time, on-focal-plane image processing using CCD (charge-coupled-device) technology is presented. In particular, an implementation for edge detection is described. Slight modification of the edge detection implementation yields an image reconstruction processor. Simulations of the image processing capabilities of the CCD processor architecture are presented
Keywords
CCD image sensors; computerised picture processing; parallel architectures; pipeline processing; charge coupled device architecture; edge detection; focal plane image signal processing; image processing capabilities; image reconstruction processor; parallel architecture; pipelined architecture; Bandwidth; Charge-coupled image sensors; Clocks; Computer architecture; Concurrent computing; Image edge detection; Image processing; Shift registers; Signal processing; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location
Taipei
Type
conf
DOI
10.1109/VTSA.1989.68627
Filename
68627
Link To Document