Designing with intellectual property

A methodology was developed based on IP reuse, aimed at the design of integrated micro-systems. It was tested on a specific custom ASIP (application specific instruction processor) with good performance. IP occurrences are searched and identified inside the system specification code (C has been used for test), before any architectural or partitioning choice is done. Isolation criteria are their reusability, encapsulation and completeness, while their C++ models are deliberately kept as mutually nestable objects arranged in a number of hierarchical levels. Each such WARELET can be instantiated to full HW instance (like a black box), or full software procedure, or a mix. Every alternative choice gives an IP instance (IPI) whose reuse value is keyed in the IP model and in the parametric synthesis procedures attached to it not in a single specific implementation The collection of WARELET instances builds up the specific system instance. The design process is a “what-if”: inside the code describing a (sub)system some selected warelets are attributed to a HW implementation. HW synthesis generates blocks that communicate within a pre-defined parametric architectural harness either as coprocessors or as execution units of the instruction set. A parallel stepwise co-synthesis is operated for SW code, re-targeting the microprogram control code and the SW algorithm to every new HW configuration. A profiling process gives performance figures to validate or change the choice. These system-level IPs offer innovative opportunities concerning the management of intellectual value within products and the commercial and industrial infrastructure