Selective clock gating by using wasting toggle rate

In this paper, we propose a RT level power reduction scheme which can be used for any applications that have power problem when designers use traditional design flow. A novel wasting-toggle-rate based clock power reduction technique is introduced and verified along with traditional design flow. The proposed technique can choose optimal clock-gating style selectively to minimize the power based on proposed wastingtoggle-rate analysis at RT level, and the optimization is based on proposed power equations without simulating the design at gate level. We have tested the proposed technique on real industrial multimedia-mobile-processor design. For the accuracy of the power optimization results, all of them are measured at gate level after synthesis by using industrial 65 nanometer technology library. The experimental results show that the technique reduces average 35.84% power comparing with non-clock gating design and 19.28% power comparing with clock-gating design by Power Compiler. The design overhead of the proposed technique is 1.79% increase of area and 2.55% increase of the critical path delay for whole circuit comparing with the original circuit.