MSDCT Architecture Implementation with DA Based Optimized LUT

In this paper a modified scaled discrete cosine transform hardware implementation is presented which will be further utilized in video chip application. The hardware design is based on the description of the algorithm along with the proof of operational steps to complete inner product operation required for discrete cosine transform (DCT) application. This paper highlights and compares 8 times 8 pixels block DCT architecture of conventional design with our optimized design. Optimized hardware is presented by virtue of distributed arithmetic (DA) and contains multiplications based on computational sharing multiplier (CSHM) concept. DA is utilized for LUT size optimization which helps to keep the area of chip and complexity of connections reasonably small