Implementation and evaluation of pattern classification architectures using transputer arrays

The paper focusses on the problem of transputer-based implementation of algorithms for pattern classification. Specifically, it shows that a very close relationship can be established between the conceptual level at which a classifier architecture is conceived and the physical level at which implementation is achieved, to the extent that novel conceptual structures can be evolved directly from a consideration of the computational characteristics identified at the physical level. This principle is demonstrated with respect to a transputer-based infra-structure which can directly exploit the inherent parallelism in most classification algorithms