System structure for FPGA-based SOPC design using hard tasks

In this paper, the authors present a system structure for FPGA-based SOPC (system on programmable chip) design which uses an embedded processor to do scheduling to the HDL modules as its hard tasks. This kind of structure is implemented on the NIOS-II system offered by ALTERA and uses muC/OS-II as a real-time kernel in the embedded soft processor. The structure of the system is introduced in details on hard tasks, resources, processor and their relationships. A video capture card which is used for medical video capture and processing is also presented as an example to show the implementation and advantage of the structure for a complex embedded system.