Scan synthesis for one-hot signals

Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot signals. In a scan-based design, one-hot values on these signals may not be maintained during the scan-in and scan-out operations. Also, the presence of faults, the existence of don´t care conditions and the use of random patterns for testing the circuit in a scan or BIST environment may lead to non-one-hot values on these one hot signals, resulting in abnormal circuit behavior and possible circuit damage. In this paper, we present new techniques for synthesizing scan-based designs so that one-hot values are maintained on the one-hot signals during all modes of operation. One of our synthesis techniques often generates designs with no area overhead-the designs are smaller than those that do not ensure safe scan operation. In addition, we propose a scan path design that has no performance overhead during the normal mode of operation and ensures that only valid states appear on the bistables during test mode, thus guaranteeing safe scan operations