A scalable and multiplier-less fully-pipelined architecture for VLSI implemetation of discrete Hartley transform [implemetation read implementation]

This paper presents a fully pipelined high-throughput, low-latency, multiplier-less architecture for VLSI implementation of the discrete Hartley transform (DHT). The structure is highly modular and scalable to accommodate higher transformation lengths, and so also it is suitable for low-hardware implementation when throughput requirement is not very high. Apart from that, the proposed structure offers significantly better speed performance and involves considerably less hardware compared with the existing structures.