Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

Author

Keshk, Arabi ; Miura, Yukiya ; Kinoshita, Kozo

Author_Institution

Grad. Sch. of Eng., Osaka Univ., Japan

fYear

2000

fDate

2000

Firstpage

120

Lastpage

124

Abstract

This paper presents an efficient procedure to improve logic testing for bridging faults (BF) in CMOS circuits. A unified procedure is presented that extracts the test vector from transistor level networks, which will reduce the occurrence of intermediate voltage that leads to Byzantine General´s problems and feedback oscillation. By using this procedure according to fault location, the fault coverage of logic testing will increase without using both simulation and a complex calculation for predicting bridging voltage or logic threshold of the driven gates

Keywords

CMOS digital integrated circuits; circuit oscillations; fault location; integrated circuit testing; logic testing; Byzantine General´s problems; CMOS circuits; bridging fault; fault coverage; feedback oscillation; logic testing; logic threshold; test vector; transistor level networks; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Feedback; Logic testing; Predictive models; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893613

Filename

893613