DocumentCode
275355
Title
Memory, control and communications synthesis for scheduled algorithms
Author
Grant, Douglas M. ; Denver, P.B.
Author_Institution
Dept. of Electr. Eng., Edinburgh Univ., UK
fYear
1990
fDate
24-28 Jun 1990
Firstpage
162
Lastpage
167
Abstract
A problem of memory allocation for intermediate variables in an ASIC synthesis system is addressed. A method is explored of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimized. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimization are illustrated with an example
Keywords
application specific integrated circuits; circuit CAD; storage allocation; ASIC synthesis system; communication optimization; communications synthesis; control optimisation; control synthesis; hardware-constrained schedule; intermediate variables; memory allocation; memory requirements; memory synthesis; scheduled algorithms; Communication system control; Costs; Delay; Hardware; Memory management; Read-write memory; Registers; Research initiatives; Scheduling algorithm; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114848
Filename
114848
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