DocumentCode
275378
Title
Algorithms for library-specific sizing of combinational logic
Author
Chan, Pak K.
Author_Institution
Comput. Eng.., California Univ., Santa Cruz, CA, USA
fYear
1990
fDate
24-28 Jun 1990
Firstpage
353
Lastpage
356
Abstract
Examined is a problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. It is shown that, if the Boolean network has a tree topology, there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated
Keywords
Boolean functions; combinatorial circuits; logic CAD; trees (mathematics); Boolean network; backtracking-based algorithm; cell library; combinational logic; library-specific sizing; logic elements; propagation delay; pseudo-polynomial time algorithm; timing constraints; tree topology; Boolean functions; Clocks; Computer networks; Constraint optimization; Cost function; Libraries; Logic; Propagation delay; Timing; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114881
Filename
114881
Link To Document