DocumentCode
2753984
Title
Process-Integration Challenges with Up-To-Date Modulation of Scaling Laws
Author
Nakai, Satoshi
Author_Institution
Dept. of Process Integration, Fujitsu Ltd., Kuwana
fYear
2006
fDate
10-13 Oct. 2006
Firstpage
1
Lastpage
3
Abstract
CMOS scaling laws have already lost the physical bases, and the merest results induced by scaling laws are still utilized for requirements from technology users. In this paper, the actual situation of CMOS shrinkage and a forecast are discussed
Keywords
CMOS integrated circuits; CMOS scaling laws; CMOS shrinkage; process-integration challenges; CMOS technology; Copper; Degradation; Guidelines; High K dielectric materials; High-K gate dielectrics; Integrated circuit interconnections; Integrated circuit technology; Voltage; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Thermal Processing of Semiconductors, 2006. RTP '06. 14th IEEE International Conference on
Conference_Location
Kyoto
Print_ISBN
1-4244-0648-X
Electronic_ISBN
1-4244-0649-8
Type
conf
DOI
10.1109/RTP.2006.367974
Filename
4223101
Link To Document