• DocumentCode
    275416
  • Title

    A fault analysis method for synchronous sequential circuits

  • Author

    Kuo, T.Y. ; Wang, J.F. ; Lee, J.Y.

  • Author_Institution
    Inst. of Electr. & Comput. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    1990
  • fDate
    24-28 Jun 1990
  • Firstpage
    732
  • Lastpage
    735
  • Abstract
    A new fault analysis method for synchronous sequential circuits is presented. Using the iterative array method, extended forward propagation and backward implication are performed, based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of tested or untestable lines. Examples are given to demonstrate the ability of the method
  • Keywords
    logic testing; sequential circuits; fault analysis method; initialization sequence; iterative array; stuck fault; synchronous sequential circuits; Circuit analysis computing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Councils; Fault diagnosis; Logic; Sequential circuits; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
  • Conference_Location
    Orlando, FL
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-363-9
  • Type

    conf

  • DOI
    10.1109/DAC.1990.114950
  • Filename
    114950