Synthesis and physical design of DLX RISC processor

Author

Al-Mohandes, Ibrahim H. ; Shed, Ali M. ; Ragaie, H.F. ; Elsaid, M.K.

Author_Institution

Fac. of Eng., Al-Azhar Univ., Cairo, Egypt

fYear

1999

fDate

23-25 Feb 1999

Abstract

A VHDL synthesizable model for AutoLogic II is developed for an unpipelined version of the 32-bit DLX RISC processor, called DLXS. The VHDL RTL model is synthesized, optimized, simulated, and laid out using Mentor Graphics EDA tools. The designed ASIC is based on the CMOSN standard cell library with 0.8 μm technology. The processor clock frequency is 33 MHz and the chip area is 8.7×9.2 mm²

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit simulation; hardware description languages; integrated circuit layout; microprocessor chips; reduced instruction set computing; 0.8 micron; 32 bit; 33 MHz; ASIC; AutoLogic II; CMOSN standard cell library; DLX RISC processor synthesis; DLXS; Mentor Graphics EDA tools; VHDL RTL model; VHDL synthesizable model; chip area; circuit layout; clock frequency; optimization; physical design; simulation; Application specific integrated circuits; CMOS technology; Clocks; Electronic design automation and methodology; Frequency; Graphics; Logic testing; Read only memory; Reduced instruction set computing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 1999. NRSC '99. Proceedings of the Sixteenth National

Conference_Location

Cairo

Print_ISBN

977-5031-62-1

Type

conf

DOI

10.1109/NRSC.1999.760910

Filename

760910