Emulation engine for spiking neurons and adaptive synaptic weights

The simulation of pulse-coded neural networks (PCNNs) for the evaluation of a biology-oriented image processing performed on general-purpose computers, e. g. PCs or workstations, is still very time-consuming. The main bottle-neck during the simulation is the sequential access to the weight memory for the calculation of the neuron states. A field-programmable gate array (FPGA) based emulation engine, called spiking neural network emulation engine (SEE), for spiking neurons and adaptive synaptic weights is presented, that tackles this bottle-neck problem by providing a distributed memory architecture and a high bandwidth to the weight memory. In addition, separated calculations of neuron states and network topology are realized and mapped to dedicated FPGAs. With this approach, an effective parallelization of the simulation algorithm is obtained. It is evaluated that the current implementation of SEE operating at a frequency of 50 MHz achieves an acceleration factor of 30 for sparsely connected networks (4- and 8-nearest-neighbor connection schemes) compared to a software implementation running on a stand-alone PC (2.4 GHz CPU and 1 GB RAM main memory).