• DocumentCode
    2755576
  • Title

    Customized Algorithms for High Performance Memory Test in Advanced Technology Node

  • Author

    Chen, Shomo ; Huang, Ning ; Tai, Ting-Pu ; Niu, Actel

  • Author_Institution
    Trident Microsyst. Inc., Santa Clara, CA, USA
  • fYear
    2009
  • fDate
    23-26 Nov. 2009
  • Firstpage
    87
  • Lastpage
    89
  • Abstract
    This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy. BIST test algorithm was used in order to address new defect mechanisms emerging at advanced process nodes.
  • Keywords
    application specific integrated circuits; built-in self test; integrated circuit testing; ASIC vendors; BIST test algorithm; IC testing strategy; customized memory test algorithms; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Decoding; Fault detection; Geometry; Integrated circuit testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2009. ATS '09.
  • Conference_Location
    Taichung
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3864-8
  • Type

    conf

  • DOI
    10.1109/ATS.2009.41
  • Filename
    5359398
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2755576