Utilizing clock skew for timing reliability improvement

In this paper, we focus on increasing the timing reliability of a circuit by exploiting the permissible clock skew range of each local data path. Our optimization goal is to maximize the tolerance of the circuit to process variations. Given an initial clock tree, which is synthesized by a commercially available layout tool, a simulated evolution approach is proposed to optimize the clock tree design such that the timing reliability is maximized. For the need of timing closure, our design methodology is to construct the reliability- driven non-zero skew clock tree at the ECO (Engineering Change Order) stage. Benchmark data consistently shows that our approach achieves very good results.