Iterative improvement based multi-way netlist partitioning for FPGAs

This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed by Kuznar et al. (1995), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques. The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of the classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results, and even outperforms them for the largest benchmarks.