Package design optimization for efficient on-chip-capacitance leveraging

This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-chip capacitance (Cdie). Three packages were used to examine how Cdie would vary when selected power rails were merged on package. The first package carries isolated power rails where each and every power rails are separated. The second package combines IO power rails which were adjacent to each other, and the third package combined all common voltage power rails across the entire chip. The Cdie contributed from each I/O buffers as well as Core were measured and compared with the Cdie on the first package design; where all power rails were isolated. It was found that not 100% of the Cdie is visible when the power rails were merged. For example: the design allocated 100nF of Cdie in the silicon; however, only 66nF is measured on a merged-power-rail-package as oppose to 100nF Cdie is measured on the standard standalone-power-rail-package design. As much as 15% - 44% Cdie was found missing on a merged power rails compare to the original Cdie build in. This paper will describe a methodology to measure and characterize the Cdie, and propose a design guideline to suggest the best way to design a package to ensure that the Cdie is properly leveraged across when a power rail merger is implemented.