An ultra low power digitally controlled oscillator with low jitter and high resolution

Author

Majd, Nasser Erfani ; Lotfizad, Mojtaba ; Abadian, Arash ; Ghoushchi, Mohammad Bagher Ghaznavi

Author_Institution

Dept. of Electr. & Comput. Eng., Tarbiat Modares Univ. (TMU), Tehran, Iran

fYear

2010

fDate

4-6 Dec. 2010

Firstpage

336

Lastpage

340

Abstract

In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 31ps and the power consumption is 0.5677mW at 750MHz with 1.2V power supply and 0.53-ps resolution. The proposed DCO has a good robustness to voltage and temperature variations and better linearity comparing to the conventional design.

Keywords

CMOS integrated circuits; Monte Carlo methods; low-power electronics; radiofrequency oscillators; CMOS predictive transistor model; Monte Carlo simulation; frequency 550 MHz to 830 MHz; low jitter CMOS design; low power Schmitt trigger based inverters; power 0.5677 mW; ring oscillator; size 32 nm; time 0.53 ps; time 31 ps; ultra low power digitally controlled oscillator; voltage 1.2 V; word length 12 bit; Computer architecture; Delay; Microprocessors; Oscillators; Phase locked loops; Power demand; Semiconductor device modeling; digitally controlled oscillator (DCO); jitter; linearity; low power; robust;

fLanguage

English

Publisher

ieee

Conference_Titel

Telecommunications (IST), 2010 5th International Symposium on

Conference_Location

Tehran

Print_ISBN

978-1-4244-8183-5

Type

conf

DOI

10.1109/ISTEL.2010.5734048

Filename

5734048