LOGO overcome combinational logic limitations

The VLSI/ULSI performance is expected to keep improving at the current rate indefinitely as feature size shrinks; however as chips are bursting with huge number of transistors, the interchip connections are increased and heat dissipation is becoming an enormous problem as more and more functions are gathered on the same chip. This will influence size and performance of chips. LOGO (logic oriented) neural network are presented as a solution. The LOGO neural network is a modeling system aimed to optimize and to improve the parallelism of logical networks; it is able to perform several independent computations in parallel by a single network. LOGO neural networks, powerful tools in both binary and multi-valued logic, are used in this paper to implement multi-valued logic circuits. These networks are designed and optimized using Reed Muller algebra and simplification methods. All these networks are simulated using MATLAB Simulink and showed successful results. These neural networks are proved to overperform ordinary combinational logic networks