Multirate Digital Phase-Lock Loops with Random Processor Latency

A critical function required in most all digital communication systems is synchronization. Three levels of synchronization include carrier phase, spreading code timing, and symbol timing estimation. Digital phase phase-locked loops (DPLLs), are often used to implement these functions. Multirate DPLLs are often found in practice where the timing error detector (TED) or phase detector (PD) operates at a much higher sampling rate than is required to operate the loop filter. It is assumed that there is an architecture partition between the TED and loop filter, the former is in firmware, while the latter runs in software on a real-time operating system (RTOS). Processor latency, which has a certain randomness to it, introduces time delay in the closed-loop system. The impact of random processor latency on loop stability and overall DPLL performance in noise and signal Doppler is studied in this paper.