A novel linear polar transmitter architecture using low-power analog predistortion for EDGE applications

This paper presents a new polar transmitter architecture that employs analog predistortion to provide substantially instantaneous correction of amplitude and phase errors in RF PAs. This approach enables to enhance the linear output power capability and efficiency of a PA, simultaneously. Unlike conventional architectures using a closed-loop feedback, no downconversion receiver is included in the transmitter. Moreover, only even-order distortion components are used to predistort the input signal in a multiplicative manner so that the effective correction bandwidth is greatly enhanced. For validation of the architecture, a PA circuit model was designed, based upon the TSMC 0.18-um CMOS technology. In the simulation results, the proposed architecture reduced PA nonlinearity from 2 dB to 0.5 dB for gain and from 18deg to plusmn0.5deg for phase. Also, the simulation results exhibited EVMs of less than 0.5% in RMS and 5% in peak, a PAE of 58% at the output power of 33 dBm.