Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?

This paper reflects on some recent results that show the value of delay-fault tests on a deep sub-micron process. However, the results also suggest that untargetted test patterns perform almost as well as those targetted on a transition fault model, despite appearing to have a much lower fault coverage. This leads to an examination of the defect mechanisms in deep sub-micron ICs, in particular the relationship of crosstalk and power-rail coupling to resistive opens and resistive bridges. A number of new fault mechanisms are described. The paper shows the importance of initialization conditions for resistive opens and the importance of noise margins with resistive bridges. These noise margin considerations throw doubts on the idea used by other authors of the “critical resistance” of a bridge