Combinational logic synthesis for diversity in duplex systems

Author

Mitra, Subhasish ; McCluskey, Edward J.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

fYear

2000

fDate

2000

Firstpage

179

Lastpage

188

Abstract

We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse duplex systems in the presence of common-mode failures. Data integrity means that the system either produces correct outputs or indicates errors when incorrect outputs we produced. Design diversity has long been used to increase the data integrity of duplex systems against common-mode failures. The conventional notion of diversity is qualitative and relies on “independent” generation of “different” implementations. In a recent paper, we presented a metric to quantify, diversity among several designs. Our synthesis techniques described in this paper use the diversity metric as a cost function and maximize diversity while reducing the area overhead of the resulting diverse duplex system

Keywords

combinational circuits; data integrity; fault diagnosis; high level synthesis; optimisation; combinational logic circuits; combinational logic synthesis; common-mode failures; cost function; data integrity; design diversity; diverse duplex system; diverse duplex systems; diversity metric; fault tolerance; multilevel logic synthesis; synthesis; two level synthesis; Circuit faults; Circuit synthesis; Combinational circuits; Cost function; Cyclic redundancy check; Error correction; Hardware; Logic design; Logic functions; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894205

Filename

894205