Strained-SOI/SGOI Dual Channel CMOS Technology Based on Ge Condensation Technique

Author

Tezuka, Taro ; Nakaharai, Shu ; Moriyama, Y. ; Hirashita, N. ; Toyoda, E. ; Numata, T. ; Irisawa, T. ; Usuda, Koji ; Sugiyama, N. ; Mizuno, Takayuki ; Takagi, S.I.

Author_Institution

MIRAI-ASET, Kawasaki

fYear

2006

fDate

15-17 May 2006

Firstpage

1

Lastpage

2

Abstract

In this paper, fabrication of the dual channel CMOS devices based on the Ge-condensation technique is demonstrated as well as their mobility and current drive enhancements. Ge-rich strained SGOI pMOSFETs were integrated with strained Si/SGOI nMOSFETs by a CMOS process combined with the Ge condensation process, in which the strain in the SGOI layers were properly controlled. As a result, significant electron- and hole-mobility enhancements for the strained SOI and SGOI channels were observed as well as I_d enhancements

Keywords

Ge-Si alloys; MOSFET; condensation; electron mobility; elemental semiconductors; germanium; hole mobility; silicon; silicon-on-insulator; Ge condensation; current drive enhancement; dual channel CMOS devices; electron mobility enhancement; hole mobility enhancement; strained SOI/SGOI; CMOS process; CMOS technology; Capacitive sensors; Fabrication; Germanium silicon alloys; MOSFETs; Oxidation; Silicon germanium; Silicon on insulator technology; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International

Conference_Location

Princeton, NJ

Print_ISBN

1-4244-0461-4

Type

conf

DOI

10.1109/ISTDM.2006.246515

Filename

1716009