Projecting the reliability of SiGe NPN transistors after AC Vbe reverse stress from DC device lifetime

The degradation of common-emitter current gain, h_FE after reverse base-emitter bias (Vbe) stress has already been attracted attention, because over the period of stress the base-emitter passivation is characterized fir its susceptibility to interface trap generation. During the Vbe reverse stress a decrease of h_FE is observed. In this study power SiGe heterojunction bipolar transistors from a state of the art BiCMOS technology were employed. All experiments were carried out at an ambient temperature of T= 25°C; with the collector shorted to base and a negligible collector current. First, DC experiments were performed and the time and voltage dependencies of the degradation were identified. By using a "reduced time model", presented in this study, the expected degradation after AC Vbe reverse stress is calculated. The experiments with an AC Vbe stress show a very good agreement between simulation and data. Also the experiments reveal that there is no frequency dependence of the h_FE-shift. Further on it is shown that a short additional forward biasing of the base-emitter junction does not relax the degradation. However, considering AC voltages the predicted operation lifetime without any reliability risk increase by more than a decade compared to the prediction from DC voltage stress.