DocumentCode
2768252
Title
Performance reliability trade-offs on high speed Si-Ge BiCMOS
Author
O´Connel, B. ; Chaparala, Prasad ; Mehrota, B.
Author_Institution
Nat. Semicond., Santa Clara, CA, USA
fYear
2003
fDate
20-23 Oct. 2003
Firstpage
52
Lastpage
55
Abstract
This work investigates several gate oxides reliability-performance tradeoffs in the architecture design of a high speed BiCMOS process. Reliability concerns arise due to often conflicting requirements of MOS and bipolar devices. The many extra bipolar process steps that are added in order to realize both MOS and bipolar device types, thermal constraints, as well as many extra plasma process steps impact gate-oxide integrity (GOI).
Keywords
BiCMOS integrated circuits; Ge-Si alloys; high-speed integrated circuits; integrated circuit design; performance evaluation; semiconductor device reliability; MOS device; bipolar device; gate oxides; high speed BiCMOS; impact gate-oxide integrity; plasma process; reliability-performance tradeoffs; thermal constraints; Annealing; BiCMOS integrated circuits; Boron; MOS capacitors; MOS devices; Plasma applications; Plasma devices; Plasma temperature; Semiconductor device reliability; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2003 IEEE International
Print_ISBN
0-7803-8157-2
Type
conf
DOI
10.1109/IRWS.2003.1283300
Filename
1283300
Link To Document