• DocumentCode
    2768384
  • Title

    Pipelined Range Reduction for Floating Point Numbers

  • Author

    Jaime, Francisco J. ; Villalba, Julio ; Hormigo, Javier ; Zapata, Emilio L.

  • Author_Institution
    University of Malaga
  • fYear
    2006
  • fDate
    Sept. 2006
  • Firstpage
    145
  • Lastpage
    152
  • Abstract
    This paper presents a new pipelined architecture to deal with range reduction for floating point representation. It is based on Horner¿s scheme and a look-up table. The overall design has been optimized for a module equal to 2¿, which is the most widely used due to trigonometric functions requirements. To ensure an accuracy of one unit in the last place (ULP), a complete error propagation study has been carried out.
  • Keywords
    Computer architecture; Design optimization; Equations; Floating-point arithmetic; Hardware; Table lookup; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on
  • Conference_Location
    Steamboat Springs, CO
  • ISSN
    2160-0511
  • Print_ISBN
    0-7695-2682-9
  • Type

    conf

  • DOI
    10.1109/ASAP.2006.53
  • Filename
    4019506
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2768384