Systolic FFT Processors: Past, Present and Future

This paper reviews developments in the implementation of systolic fast Fourier transform processors over two decades (early 1980s to early 2000s) and identifies positive and negative lessons learned. The modular transform processor was developed at TRW in 1983-84. It is a set of 6 large circuit boards that computes 4096 point FFTs using 22-bit floating-point arithmetic at sustained data rates of 40 MSPS. A single chip systolic FFT developed by the Mayo Foundation in 2001-02 computes 4096 point FFTs using 16-bit fixed-point arithmetic at sustained data rates of 200 MSPS. Some thoughts on the future directions of systolic FFT processor development are offered. Future systems will compute larger FFTs at higher data rates, will employ IEEE standard floating point arithmetic and will consume less power