DocumentCode
2768430
Title
Massively parallel GOI test
Author
Ng, Tze Gong ; Lo, Keng Foo ; JIE, BinBin ; Andrew, Yap
Author_Institution
Chartered Semicond. Manuf. Ltd., Singapore
fYear
2003
fDate
20-23 Oct. 2003
Firstpage
101
Lastpage
104
Abstract
Massively parallel GOI (gate oxide integrity) Vramp tests offer a fast method, capable of testing 6 test structures on a single touchdown of the probe card. This greatly reduced total test cycle times and costs. In this work, we have done extensive testing on 0.13μm logic process on both thick/thin gate transistors (NMOS/PMOS). Comparison of single test structure testing versus massively parallel test structure testing has been done. There is no significant change in the voltage breakdown and gate leakage current parameters.
Keywords
MOSFET; leakage currents; semiconductor device breakdown; semiconductor device reliability; 0.13 micron; NMOS; PMOS; gate leakage current; logic process; massively parallel GOI Vramp tests; parallel test structures; probe card; test cycle cost; test cycle time; thick-thin gate transistors; voltage breakdown; Crosstalk; Current measurement; Dielectric breakdown; Electronic equipment testing; Gate leakage; Leakage current; Logic testing; Probes; Semiconductor device testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2003 IEEE International
Print_ISBN
0-7803-8157-2
Type
conf
DOI
10.1109/IRWS.2003.1283310
Filename
1283310
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