Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder

This paper describes the implementation of a 256-state, rate 1/2, soft-decision Viterbi decoder. The implementation explores several variables and design considerations of a Viterbi decoder, testing various methods for low power and throughput capability. By designing the Viterbi decoder using three techniques, a progressive active ACS (add-compare-select), prediction matcher, and reduced read traceback, we take the most efficient techniques and apply them, iteratively to the overall design to achieve 12.7 % of dynamic power consumption with 250Mbps of throughput