New Schemes in Clustered VLIW Processors Applied to Turbo Decoding

State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for innovative solutions. In recent years the area of application specific processors has attracted the attention of the research community and important advances have been made possible. This work introduces an ASIP architecture for SISO Turbo decoding based on a dual-clustered VLIW processor. The machine deals with instructions of up to 21 operands in an innovative way, the fetching and asserting of data is serialized and the addressing is automatized and transparent for the programmer. An optimized architecture is achieved, flexible enough to comply with leading edge standards and adaptable to demanding hardware constraints.