Multilevel synthesis minimizing the routing factor

A multilevel logic synthesis method based on standard cells and aiming at reducing both gate and wiring areas is presented. The goal is to decrease the routing factor which is defined as a ratio between the routing area and the gate area. The wiring is taken into account during the synthesis steps (factorization and technology mapping). The approach is based on a lexicographical expression of a Boolean function controlling the input dependency and on a kernel filtering controlling the excessive factorizations responsible for wiring complexity increase