Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme

To reduce both dynamic and standby power dissipation, a new 6T-based SRAM architecture is proposed. It is partitioned into an optimal number of hierarchical sub-blocks, which are selectively activated by a novel tree address decoder. Also, a new equalizer precharge scheme with reduced leakage paths is presented. Low standby power and stable access are achieved with back-biasing and other techniques. The new approach is verified in a 40-nm CMOS technology by simulation.