• DocumentCode
    2771130
  • Title

    A 10b 200MS/s pipelined folding ADC with offset calibration

  • Author

    Hsu, Cheng-Chung ; Huang, Chen-Chih ; Lin, Ying-Hsi ; Lee, Chao-Cheng

  • Author_Institution
    Hsinchu, Hsinchu
  • fYear
    2007
  • fDate
    11-13 Sept. 2007
  • Firstpage
    151
  • Lastpage
    154
  • Abstract
    A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of 10.1MHz. Fabricated in 0.35/0.13 mum CMOS, the ADC occupies an area of 0.45 mm2. The analog and digital circuits dissipate 285mW at 3.3V and lmW at 1.2V power supply, respectively.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; comparators (circuits); ADC; CMOS; comparators; frequency 10.1 MHz; offset calibration; power 1 mW; power 285 mW; power supply; voltage 1.2 V; voltage 3.3 V; word length 10 bit; Bandwidth; CMOS technology; Calibration; Capacitors; Chaotic communication; Circuits; Degradation; Engines; Frequency measurement; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
  • Conference_Location
    Munich
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4244-1125-2
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2007.4430268
  • Filename
    4430268
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2771130