DocumentCode
2772695
Title
Delay time constant analysis for fτ optimization in RF Si/SiGe bipolar devices
Author
Sun, I.-S.M. ; Xu, H.E. ; Tam, R. ; Ng, W.T. ; Mochizuki, H. ; Toita, M. ; Kobayashi, T. ; Furukawa, Y. ; Imai, H. ; Ishikawa, A. ; Saito, N. ; Ueda, Y. ; Ueshima, Y. ; Tamura, S. ; Takasuka, K. ; Kohno, T. ; Soga, S. ; Sako, K. ; Imai, H.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
323
Lastpage
326
Abstract
This work describes an approach for fτ optimization in RF Si/SiGe bipolar devices by analyzing the delay time components that contribute to the overall transistor speed. Using the proposed parameter extraction method, all delay time constants can be obtained. Subsequently, identifying and minimizing the limiting time delay can effectively improve fτ of the bipolar devices. Using AKM´s Si-BJT technology as a case study, the optimization of the SiGe epitaxial base, intrinsic collector and base doping profiles, and extrinsic collector resistance is demonstrated.
Keywords
Ge-Si alloys; bipolar transistors; delay circuits; doping profiles; elemental semiconductors; semiconductor device models; semiconductor epitaxial layers; silicon; RF Si/SiGe bipolar devices; Si-BJT technology; Si-SiGe; SiGe epitaxial layer; delay time components; delay time constant analysis; doping profiles; extrinsic collector resistance; intrinsic collector; optimization RF Si/SiGe bipolar devices; transistor speed; CMOS process; CMOS technology; Costs; Delay effects; Equations; Germanium silicon alloys; Heterojunction bipolar transistors; Radio frequency; Silicon germanium; Sun;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283541
Filename
1283541
Link To Document