• DocumentCode
    2775189
  • Title

    On the Reliability of Four Full Adder Cells

  • Author

    Ibrahim, W. ; Beiu, V. ; Alkhawwar, Y.A.

  • Author_Institution
    College of Information Technology, United Arab Emirates University, Al Ain, United Arab Emirates. walidibr@uaeu.ac.ae, 200000236@uaeu.ac.ae
  • fYear
    2007
  • fDate
    18-20 Nov. 2007
  • Firstpage
    720
  • Lastpage
    724
  • Abstract
    This study presents a top-down investigation of the reliability of four different fall adder (FA) designs. It provides insights into different parameters that affect the reliability of these FAs. The probability transfer matrix (PTM) approach is used to numerically estimate the reliability of the FAs under investigation. Simulation results show that the FAs´ reliabilities depend not only on the numbers of gates, but also on the types of gates used as well as on the way these gates are interconnected. The simulation results also show how different gates affect the FAs´ reliabilities and are extended with estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).
  • Keywords
    Adders; Arithmetic; Birth disorders; Circuits; Digital signal processing; Energy consumption; Logic devices; Microprocessors; Nanoscale devices; Numerical models; Fault/defect tolerance; full adder; probabaility transfer matrix (PTM); reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovations in Information Technology, 2007. IIT '07. 4th International Conference on
  • Conference_Location
    Dubai, United Arab Emirates
  • Print_ISBN
    978-1-4244-1840-4
  • Electronic_ISBN
    978-1-4244-1841-1
  • Type

    conf

  • DOI
    10.1109/IIT.2007.4430508
  • Filename
    4430508