Error-resilient design of branch predictors for effective yield improvement

Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor´s performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.