DocumentCode
2777377
Title
Finite Element Analysis of Dynamic Drop Impact of Board-level Stacked-Die Packages Using Submodeling Technique
Author
Hsu, Hsiang-Chen ; Hsu, Yu-Chia ; Lee, Hui-Yu ; Yeh, Chang-Lin ; Lai, Yi-Shao ; Fu, Shen-Li
Author_Institution
I-Shou Univ., Kaohsiung
fYear
2006
fDate
11-14 Dec. 2006
Firstpage
1
Lastpage
8
Abstract
The objective of this research is to investigate the effects of board-level drop test based on the support excitation scheme incorporated with the submodel technique for stacked-die packages. Three lead-free materials, namely SAC405 (Sn4Ag0.5Cu), SAC387(Sn3.8Ag0.7Cu) and Sn3.5Ag were used to demonstrate the transient dynamic response for solder balls subject to JEDEC pulse-controlled board-level drop test standard JESD22-B110A Condition B[1]. The support excitation scheme was developed and applied to examine the transient dynamic response for it produces no rigid-body motion to the test vehicle and dramatically reduces the computational cost. In order to evaluate the structure of the interested area, a strip model sliced from the full test vehicle is used in this research. In addition, the submodel region is particularly chosen with strip model by performing the cut boundary interpolation. The envelope of equivalent stress for the outermost solder joint off the end of the strip model is plot to show the potential solder failure mode and mechanism. The cut boundary of submodel is verified and the mesh density of submodel is examined. For a refinery mesh of submodel, parametric studies are carried out to study the reliability of the outermost solder joint, and the results are summarized as design rules for the development of stacked-die packages.
Keywords
electronics packaging; finite element analysis; soldering; solders; transient response; board-level stacked-die packages; computational cost reduction; dynamic drop impact; finite element analysis; lead-free materials; mesh density; solder balls; solder joint equivalent stress; submodeling technique; transient dynamic response; Computational efficiency; Environmentally friendly manufacturing techniques; Finite element methods; Lead; Materials testing; Packaging; Soldering; Strips; Vehicle dynamics; Vehicles; cut boundary; pulse-controlled board-level drop test; stacked-die; submodeling technique; support excitation scheme;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on
Conference_Location
Kowloon
Print_ISBN
978-1-4244-0834-4
Electronic_ISBN
978-1-4244-0834-4
Type
conf
DOI
10.1109/EMAP.2006.4430622
Filename
4430622
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